View ADSP-21MSP58_3624478.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

functional block diagram memory program memory 4k x 24 (rom) adsp-21msp59 program memory 2k x 24 data memory 2k x 16 ADSP-21MSP58/59 alu mac shifter arithmetic units external address bus external data bus host interface port serial ports sport 0 sport 1 timer dag 1 dag 2 data address generators program sequencer powerdown control logic flag data memory data data memory address program memory address analog interface adsp-2100 base architecture program memory data rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a dsp microcomputers ADSP-21MSP58/59 ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features 38 ns instruction cycle time (26 mips) from 13.00 mhz crystal adsp-2100 family code and function compatible with new instruction set enhanced for bit manipulation instructions, multiplication instructions, biased rounding, and global interrupt masking 2k 3 24 words of on-chip program memory ram 2k 3 16 words of on-chip data memory ram 4k 3 24 words of on-chip program memory rom (adsp-21msp59 only) 8-bit parallel host interface port analog interface provides: 16-bit sigma-delta adc and dac programmable gain stages on-chip anti-aliasing & anti-imaging filters 8 khz sampling frequency 65 db adc, snr and thd 72 db dac, snr and thd 425 mw typical power dissipation @ 5.0 v @ 38 ns <1 mw powerdown mode with 100 cycle recovery dual purpose program memory for both instruction and data storage independent alu, multiplier/accumulator, and barrel shifter computational units two independent data address generators powerful program sequencer provides: zero overhead looping conditional instruction execution two double-buffered serial ports with companding hardware, one serial port (sport0) has automatic data buffering programmable 16-bit interval timer with prescaler programmable wait state generation automatic booting of internal program memory from byte-wide external memory, e.g., eprom, or through host interface port stand-alone rom execution (adsp-21msp59 only) single-cycle instruction execution single-cycle context switch multifunction instructions three edge- or level-sensitive external interrupts low power dissipation in standby mode 100-lead tqfp general description the ADSP-21MSP58 and adsp-21msp59 mixed-signal pro- cessors (msprocessor ? dsps) are fully integrated, single-chip dsps complete with a high performance analog front end. the ADSP-21MSP58/59 family is optimized for voice band applica- tions such as speech compression, speech processing, speech recognition, text-to speech, and speech-to-text conversion. the ADSP-21MSP58/59 combines the adsp-2100 base archi- tecture (three computation units, data address generators, and program sequencer) with two serial ports, a host interface port, an analog front end, a programmable timer, extensive interrupt capability, and on-chip program and data memory. the ADSP-21MSP58 provides 2k words (24-bit) of program ram and 2k words (16-bit) of data memory. the adsp- 21msp59 provides an additional 4k words (24-bit) of program rom. the ADSP-21MSP58/59 integrates a high performance analog codec based on a single chip, voice band codec, the ad28msp02. powerdown circuitry is also provided to meet the low power needs of battery operated portable equipment. the ADSP-21MSP58/59 is available in a 100-pin tqfp package (thin quad flat package). in addition, the ADSP-21MSP58/59 supports new instructions, which include bit manipulationsCbit set, bit clear, bit toggle, bit testCnew alu constants, new multiplication instruction (x squared), biased rounding, and global interrupt masking. msprocessor is a registered trademark of analog devices, inc.
rev. 0 C2C ADSP-21MSP58/59 digital architecture overview figure 1 is an overall block diagram of the ADSP-21MSP58/59. the processors contain three independent computational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; divi- sion primitives are also supported. the mac performs single- cycle multiply, multiply/add, and multiply/subtract operations. the shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. the shifter can be used to efficiently implement numeric format control in- cluding multiword floating-point representations. the internal result (r) bus directly connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient use of these computational units. the sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. with internal loop counters and loop stacks, the ADSP-21MSP58/59 executes looped code with zero overheadno explicit jump instructions are required to maintain the loop. two data address generators (dags) provide addresses for si- multaneous dual operand fetches (from data memory and pro- gram memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. the circular buffering feature is also used by the serial ports for automatic data transfers to (and from) on-chip memory. efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus the two address buses (pma, dma) share a single external ad- dress bus, allowing memory to be expanded off chip, and the two data buses (pmd, dmd) share a single external data bus. the bms , dms , and pms signals indicate which memory space the external buses are being used for. program memory can store both instructions and data, permit- ting the ADSP-21MSP58/59 to fetch two operands in a single cycle, one from program memory and one from data memory. the ADSP-21MSP58/59 can fetch an operand from on-chip program memory and the next instruction in the same cycle. the memory interface supports slow memories and memory- mapped peripherals with programmable wait state generation. external devices can gain control of the processors buses with the use of the bus request/grant signals ( br and bg ). bus grant has two modes of operation. if gomode is enabled in the mstat register, instruction execution continues from internal memory. if gomode is disabled, the processor stops instruction execution and waits for deassertion of br . in addition to the address and data bus for external memory connection, the ADSP-21MSP58/59 has a host interface port (hip) for easy connection to a host processor. the hip is made up of 8 data/address pins and 10 control pins. the hip is ex- tremely flexible and provides a simple interface to a variety of host processors. for example, the motorola 68000 series, the intel 80c51 series, and the analog devices adsp-2101 can be easily connected to the hip. the host processor can boot the ADSP-21MSP58/59 on-chip memory through the hip. the ADSP-21MSP58/59 can respond to eleven interrupts. there can be up to three external interrupts, configured as edge- or level-sensitive, and seven internal interrupts generated by the timer, the serial ports (sports), the hip, the powerdown cir- cuitry, and the analog interface. there is also a master reset signal. the two serial ports provide a complete synchronous serial in- terface with optional companding in hardware and a wide vari- ety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable se- rial clock or accept an external serial clock. booting circuitry provides for loading on-chip program memory automatically from byte-wide external memory. after reset, output regs input regs shifter output regs input regs alu output regs input regs mac control logic 16 r bus transmit reg receive reg serial port 0 5 companding circuitry transmit reg receive reg serial port 1 5 timer power down control logic hip control data address generator #1 data address generator #2 program rom 4k x 24 (adsp-21msp59) program sram 2k x 24 data sram 2k x 16 1 8 10 hip data bus external address bus external data bus flag dmd bus 16 24 14 14 pmd bus dma bus pma bus program sequencer boot address generator instruction register 1 adc, dac and filters 7 mux mux 14 24 hip register figure 1. ADSP-21MSP58/59 block diagram
ADSP-21MSP58/59 rev. 0 C3C seven wait states are automatically generated. this allows, for example, a 38 ns ADSP-21MSP58/59 to use a 250 ns eprom as external boot memory. multiple programs can be selected and loaded from the eprom with no additional hardware. the on-chip program memory can also be initialized through the hip. the ADSP-21MSP58/59 features a general purpose flag output whose state is controlled through software. you can use this output to signal an event to an external device. in addition, the data input and output pins on sport1 can be alternatively configured as an input and an output flag. a programmable interval timer can generate periodic interrupts. a 16-bit count register (tcount) is decremented every n cycles, where nC1 is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). the ADSP-21MSP58/59 instruction set provides flexible data moves and multifunction (one or two data moves with a compu- tation) instructions. every instruction can be executed in a single processor cycle. the ADSP-21MSP58/59 uses an alge- braic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. serial ports the ADSP-21MSP58/59 processors include two synchronous se- rial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the ADSP-21MSP58/59 sports. refer to the adsp-2100 family users manual for fur- ther details. ? sports are bidirectional with a separate, double-buffered transmit and receive section. ? sports can use an external serial clock or generate their own clock internally. ? sports have independent framing for the transmit and receive sections. sections run in a frameless mode or with frame synchronization signals internally or externally gener- ated. frame sync signals are programmed to be active high or low, with either of two pulse widths and timings. ? sports support serial data word lengths from 3 to 16 bits and provide optional a-law and m -law companding according to ccitt recommendation g.711. ? sports receive and transmit sections generate separate interrupts when the sports are ready to read or write new data. ? sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data w ord (autobuffering mode). an interrupt is generated after a complete data buffer transfer. ? sport0 has a multichannel interface to selectively receive and transmit a 24- or 32-word, time-division multiplexed serial bit stream. ? sport1 can be reconfigured as two external interrupt inputs ( irq0 and irq1 ) and the flag in and flag out signals (fi, fo). the internally generated serial clock may still be used in this configuration. pin descriptions the ADSP-21MSP58 and adsp-21msp59 are available in a 100-lead tqfp package. table i contains the pin descriptions. table i. ADSP-21MSP58/59 pin list pin # group of input/ name pins output function digital pin s address 14 o address output for program, data and boot memory spaces data 24 i/o data i/o pins for program and data memories. input only for boot memory space, with two msbs used as boot space addresses. reset 1 i processor reset input irq2 1 i external interrupt request #2 br 1 i external bus request input bg 1 o external bus grant output pms 1 o external program memory select dms 1 o external data memory select bms 1 o boot memory select rd 1 o external memory read enable wr 1 o external memory write enable mmap 1 i memory map select clkin, xtal 2 i external clock or quartz crystal input clkout 1 o processor clock output hack 1 o hip acknowledge output hsel 1 i hip select input bmode 1 i boot mode select (0 = standard eprom booting, 1 = hip booting) hmd0 1 i bus strobe select (0 = rd / wr , 1 = rw/ ds ) hmd1 1 i hip address/data mode select (0 = separate, 1 = multiplexed) hrd /hrw 1 i hip read strobe or read/write select hwr / hds 1 i hip write strobe or host data strobe select hd7C0/ had7C0 8 i/o hip data or hip data and address ha2/ale 1 i host address 2 or address latch enable ha1C0/ (unused) 2 i host address 1 and 0 inputs sport0 5 i/o serial port 0 pins (tfs0, rfs0, dt0, dr0, sclk0) sport1 5 i/o serial port 1 pins (tfs1, rfs1, dt1, dr1, sclk1) or
rev. 0 C4C ADSP-21MSP58/59 pin # group of input/ name pins output function irq0 (rfs1) 1 i external interrupt request #0 irq1 (tfs1) 1 i external interrupt request #1 sclk1 1 o programmable clock output fi (dr1) 1 i flag input pin fo (dt1) 1 o flag output pin fl0 1 o general purpose flag output pin v dd 4 digital power supply pins gnd 5 ground pins pwd 1 i powerdown pin analog pins vin norm 1 i input terminal of the norm amplifier for the encoder section (adc) vin aux 1 i input terminal of the aux amplifier for the encoder section (adc) decouple 1 i ground reference of the norm and aux amplifiers for the encoder section (adc) vout p 1 o noninverting output terminal of the differential amplifier from the decoder section (dac) vout n 1 o inverting output terminal of the differential amplifier from the decoder section (dac) v ref 1 o output voltage reference ref_ filter 1 o voltage reference external by- pass filter node v cc 1 analog power supply gnd a 2 analog ground host interface port the ADSP-21MSP58/59 host interface port (hip) is a parallel i/o port that allows for an easy connection to a host processor. through the hip, the ADSP-21MSP58/59 can be used as a memory-mapped peripheral to a host computer. the hip can be thought of as an area of dual-ported memory, or mailbox reg- isters, that allows communication between the computational core of the ADSP-21MSP58/59 and the host computer. the host interface port is completely asynchronous. the host processor can write data into the hip while the adsp- 21msp58/59 is operating at full speed. the hip can be configured with the following pins: ? bmode (when mmap = 0) determines whether the adsp- 21msp58/59 boots from the host processor (through the hip) or external eprom (through the data bus). ? hmd0 configures the bus strobes as separate read and write strobes, or a single read/write select and a host data strobe. ? hmd1 selects separate address (3-bit) and data (8-bit) buses, or a multiplexed 8-bit address/data bus with address latch enable. tying these pins to appropriate values configures the adsp- 21msp58/59 for straight-wire interface to a variety of industry- standard microprocessors and microcomputers. when the host processor writes an 8-bit value to the hip, the upper eight bits of the hip registers are all zeros. for additional information, refer to the adsp-2100 family users manual , chapter 7, for information about 8-bit configuration. hip operation the hip contains six data registers (hdr5-0) and two status registers (hsr7-6) with an associated hmask register for masking interrupts from individual hip data registers. the hip data registers are memory-mapped in the internal data memory of the ADSP-21MSP58/59. hip transfers can be managed using either interrupts or polling. these registers are shown in the sec- tion ADSP-21MSP58/59 registers. the two status registers provide status information to both the ADSP-21MSP58/59 and the host processor. hsr7 contains a software reset bit that can be set by the ADSP-21MSP58/59 and the host. the hip allows a software reset to be performed by the host processor. the internal software reset signal is asserted for five ADSP-21MSP58/59 cycles. the hip generates an interrupt whenever an hdr register re- ceives data from a host processor write. it also generates an in- terrupt when the host processor has performed a successful read of any hdr. the read/write status of the hdrs is also stored in the hsr registers. the hmask register bits can be used to mask the generation of read or write interrupts from individual hdr registers. bits in the imask register enable and disable all hip read interrupts or all hip write interrupts. so, for example, a write to hdr4 will cause an in terrupt only if both the hdr4 write bit in hmask and the hip write interrupt enable bit in imask are set. the hip provides a second method of booting the adsp- 21msp58/59 in which the host processor loads instructions into the hip. the ADSP-21MSP58/59 automatically transfers the data, in this case opcodes, to internal program memory. the bmode pin determines whether the ADSP-21MSP58/59 boots from the host processor through the hip or from external eprom over the data bus. interrupts the interrupt controller lets the processor respond to interrupts and reset with a minimum of overhead. the ADSP-21MSP58/59 provides up to three external interrupt input pins, irq0 , irq1 , and irq2 . irq2 is always available as a dedicated pin; sport1 may be reconfigured for irq1 and irq0 and the flag. the ADSP-21MSP58/59 also supports internal interrupts from the timer, the host interface port, the serial ports, the analog in- terface, and the powerdown control circuit. the interrupts are internally prioritized and individually maskable (except for powerdown and reset ). the input pins can be programmed for either level- or edge-sensitivity. the priorities and vector ad- dresses for the interrupts are shown in table ii; the interrupt registers are shown in figure 2.
ADSP-21MSP58/59 rev. 0 C5C table ii. interrupt priority & interrupt vector addresses interrupt vector source of interrupt address (hex) reset (or power-up with pucr = 1) 0000 ( highest priority ) powerdown (nonmaskable) 002c irq2 0004 hip write 0008 hip read 000c sport0 transmit 0010 sport0 receive 0014 analog interface transmit 0018 analog interface receive 001c sport1 transmit or ( irq1 ) 0020 sport1 receive or ( irq0 ) 0024 timer 0028 ( lowest priority ) interrupts can be masked or unmasked with the imask regis- ter. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected. the powerdown interrupt is non-maskable. the interrupt control register, icntl, allows the external in- terrupts to be set as either edge- or level-sensitive. interrupt ser- vice routines can either be nested (with higher priority interrupts taking precedence) or be processed sequentially (with only one interrupt service active at a time). the interrupt force and clear register, ifc, is a write-only regis- ter used to force an interrupt or clear a pending edge-sensitive interrupt. on-chip stacks preserve the processor status and are automati- cally maintained during interrupt handling. the stack is twelve levels deep to allow interrupt nesting. register bit values shown in figure 2 are the default bit values after reset. if no values are shown, the bits are indeterminate at reset. reserved bits are shown in gray; these bits should always be written with zeros. 0000000000000000 1514131211109876543210 timer sport1 receive or irq0 sport1 transmit or irq1 analog receive analog transmit sport0 receive sport0 transmit irq2 1 = enable, 0 = disable interrupt clear irq2 sport0 transmit sport0 receive analog transmit analog receive sport1 transmit or irq1 sport1 receive or irq0 timer interrupt force ifc 0000000000 9876543210 timer irq0 or sport1 receive irq1 or sport1 transmit analog receive analog transmit 1 = enable, 0 = disable irq2 hip write hip read sport0 transmit sport0 receive imask 43210 0 icntl irq0 sensitivity irq1 sensitivity irq2 sensitivity interrupt nesting 1 = edge 0 = level 1 = enable, 0 = disable figure 2. interrupt registers the following instructions allow global enable or disable servic- ing of the interrupts (including powerdown), regardless of the state of imask. disabling the interrupts does not affect autobuffering. ena ints; dis ints; interrupt servicing is enabled on processor reset. system interface figure 3 shows a basic system configuration with the adsp- 21msp58/59, two serial devices, a host processor, a boot eprom, optional external program and data memories, and an analog interface. up to 15k words of data memory and 16k words of program memory can be supported. programmable wait state generation allows the processor to interface easily to slow memories. the ADSP-21MSP58/59 also provides one ex- ternal interrupt and two serial ports or three external interrupts and one serial port. clock signals the ADSP-21MSP58/59 clkin input may be driven by a crys- tal or by a ttl-compatible external clock signal. the clkin input may not be halted, changed in frequency during operation, or operated at any frequency other the one specified. operating the ADSP-21MSP58/59 at any other fre- quency changes the analog performance, which is not tested or supported. if an external clock is used, it should be a ttl-compatible sig- nal running at half the instruction rate. the signal should be connected to the processors clkin input; in this case, the xtal input must be left unconnected. the ADSP-21MSP58/59 uses an input clock with a frequency equal to half the instruction rate; a 13 mhz input clock yields a 38.46 ns processor cycle (which is equivalent to 26 mhz). nor- mally, instructions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. the
rev. 0 C6C ADSP-21MSP58/59 clkin xtal v cc gnd a v dd gnd host mode clkout reset irq2 br bg mmap fl0 pms rd wr address data dms bms hip serial port 0 serial port 1 sclk rfs tfs dt dr sclk rfs or irq0 tfs or irq1 dt or fo dr or fi 24 14 8 7 3 5 4 4 3 2 1 hip control hip data/addr 14 2 8 ad cs oe boot memory e.g., eprom 27c64 27c128 27c256 27c512 ad cs oe we data memory & peripherals (optional) 24 16 note: the two msbs of the boot eprom address are also the two msbs of the data bus. this is only for the 27c256 and 27c512. analog input analog output clock or crystal serial device (optional) serial device (optional) host processor (optional) ad cs oe we program memory (optional) d 23-8 d 23-22 d 15-8 ADSP-21MSP58/59 figure 3. ADSP-21MSP58/59 basic system configuration clkout signal is enabled and disabled by the clkodis bit in the sport0 autobuffer control register, dm[0x3ff3]. because the ADSP-21MSP58/59 includes an on-chip oscillator circuit, an external crystal may also be used. the crystal should be connected across the clkin and xtal pins, with two ca- pacitors connected as shown in figure 4. a parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. clkin xtal clkout ADSP-21MSP58/59 figure 4. external crystal connections reset the reset signal initiates a master reset of the adsp- 21msp58/59. the reset signal must be asserted during the power-up sequence to assure proper initialization. reset dur- ing initial power-up must be held long enough to allow the processors internal clock to stabilize. if reset is asserted at any time after power-up, the clock continues to run and does not require stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is ap- plied to the processor and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 clkin cycles will ensure that the pll has locked (this does not, however, include the crystal oscillator start-up time). during this power-up sequence, the reset signal should be held low. on any subsequent resets, the reset signal must meet the minimum pulse width specification, t rsp . the reset input contains some hysteresis; however, if you use an rc circuit to generate your reset signal, the use of an ex- ternal schmidt trigger is recommended. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the mstat register. when reset is released, if there is no pending bus re- quest and the chip is configured for booting (mmap = 0), the boot loading sequence is performed. then the first instruction is fetched from internal program memory location 0x0000 and ex- ecution begins. program memory interface the on-chip program memory address bus (pma) and on-chip program memory data bus (pmd) are multiplexed with the on- chip data memory buses (dma, dmd), creating a single exter- nal data bus and a single external address bus. the data and address busses are three-stated when the dsp runs from inter- nal memory. refer to the adsp-2100 family users manual , chapter 10, memory interface for a detailed explanation. the 14-bit address bus directly addresses up to 16k words. see program memory maps for details on program memory addressing. the program memory data lines are bidirectional. the program memory select ( pms ) signal indicates access to program memory and can be used as a chip select signal. the write ( wr ) signal indicates a write operation and is used as a write strobe.
ADSP-21MSP58/59 rev. 0 C7C the read ( rd ) signal indicates a read operation and is used as a read strobe or output enable signal. an external program memory access should always be qualified with the pms signal. the ADSP-21MSP58/59 writes data from its 16-bit registers to 24-bit program memory using the px register to provide the lower eight bits. when the processor reads data (not instruc- tions) from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the px register. the program memory interface can generate zero to seven wait states for ex- ternal memory devices; the default is seven wait states after reset . program memory maps ADSP-21MSP58 ADSP-21MSP58 program memory can be mapped in two ways, depending on the state of the mmap pin. figure 5 shows the two configurations. when mmap = 0, internal ram occupies 2k words beginning at address 0x0000; external program memory uses the remaining 14k words beginning at address 0x0800. in this configuration, the boot loading sequence (de- scribed in boot memory interface) is automatically initiated when reset is released. internal ram loaded from external boot memory external external internal ram not loaded 0000 07ff 0800 3fff 0000 37ff 3800 3fff mmap=1 mmap=0 figure 5. ADSP-21MSP58 program memory maps when mmap = 1, 14k words of external program memory be- gin at address 0x0000 and internal ram is located in the upper 2k words, beginning at address 0x3800. in this configuration, the boot loading sequence does not take place; execution begins immediately after reset . adsp-21msp59 the adsp-21msp59 is functionally identical to the adsp- 21msp58. the adsp-21msp59 includes an additional 4k by 24-bit mask programmable rom (see figure 6). the rom can be used to hold program instructions or data and can be accessed twice in one instruction cycle if necessary. the rom always resides at locations pm[0x0800] through pm[0x17ff] regardless of the state of the mmap pin. sixteen addresses at the end of rom (0x17f0C0x17ff) are reserved for analog devices use. the rom is enabled by setting the romenable bit in the data memory wait state control register, dm[0x3ffe]. when the romenable bit is set to 1, addressing program memory in this range will access the on-chip rom. when set to 0, addressing program memory in this ra nge will access exter- nal program memory. the romenable bit is set to 0 on chip reset. data memory interface the data memory address bus (dma) is 14 bits wide. the bi- directional external data bus is 24 bits wide, with the upper 16 bits used for data memory data (dmd) transfers. the data memory select ( dms ) signal indicates access to data memory and can be used as a chip select signal. the write ( wr ) signal indicates a write operation and can be used as a write strobe. the read ( rd ) signal indicates a read operation and can be used as a read strobe or output enable signal. the ADSP-21MSP58/59 supports memory-mapped i/o, with the peripherals memory mapped into the data or program memory address spaces and accessed by the processor in the same manner. data memory map the on-chip data memory ram resides in the 2k words begin- ning at address 0x3000, as shown in figure 7. in addition, data memory locations from 0x3800 to the end of data memory at 0x3fff are reserved. control registers for the system, timer, internal ram loaded from external boot memory external external internal ram not loaded 0000 07ff 0800 3fff 0000 07ff 0800 3fff rom enable = 1 mmap = 0 external external internal ram not loaded 0000 37ff 3800 3fff 0000 37ff 3800 3fff internal mask programmed rom 17ff 1800 17f0 ?17ff reserved 07ff 0800 17ff 1800 internal ram loaded from external boot memory internal mask programmed rom 17f0 ?17ff reserved rom enable = 0 mmap = 0 rom enable = 1 mmap = 1 rom enable = 0 mmap = 1 external figure 6. adsp-21msp59 program memory maps
rev. 0 C8C ADSP-21MSP58/59 wait-state configuration, host interface port, codec, and serial port operations are located in this region of memory. the remaining 12k of data memory is external. external data memory is divided into three zones, each associated with its own wait-state generator. by mapping peripherals into different zones, you can accommodate peripherals with different wait- state requirements. all zones default to seven wait states after reset . for compatibility with other adsp-2100 family processors, bit definitions for dwait3 and dwait4 are shown in the data memory wait state control register, but they are not used by the ADSP-21MSP58/59. 12k external memory mapped registers and reserved 0000 07ff 0800 3fff 0000 37ff 3800 3fff data memory wait states dwait0 (1k external) dwait1 (1k external) dwait2 (10k external) no wait states 03ff 0400 2fff 3000 2k internal 1k reserved 2fff 3000 3bff 3c00 figure 7. ADSP-21MSP58/59 data memory maps boot memory interface the ADSP-21MSP58/59 can load on-chip memory from exter- nal boot memory space. the boot memory space consists of 64k by 8-bit space, divided into eight separate 8k by 8-bit pages. three bits in the system control register select which page is loaded by the boot memory interface. another bit in the system control register allows the user to force a boot loading sequence under software control. boot loading from page 0 after reset is initiated automatically if mmap = 0. the boot memory interface can generate zero to seven wait states; it defaults to seven wait states after reset . this allows the ADSP-21MSP58/59 to boot from a single low cost eprom such as a 27c256. program memory is booted one byte at a time and converted to 24-bit program memory words. the bms and rd signals are used to select and to strobe the boot memory interface. only 8-bit data is read over the data bus, on pins d8Cd15. to accommodate addressing up to eight pages of boot memory, the two msbs of the data bus are used in the boot memory interface as the two msbs of the boot memory address. the adsp-2100 family assembler and linker support the cre- ation of programs and data structures requiring multiple boot pages during execution. rd and wr must always be qualified by pms , dms , or bms to ensure the correct program, data, or boot memory accessing. hip booting the ADSP-21MSP58/59 can also boot programs through the host interface port. if bmode = 1 and mmap = 0, the ADSP-21MSP58/59 boots from the hip. if bmode = 0, the ADSP-21MSP58/59 boots through the data bus (in the same way as the adsp-2101), as described above in boot memory interface. for additional information about hip booting, refer to the adsp-2100 family users manual , chapter 7, host in- terface port. the adsp-2100 family development software includes a utility program called the hip splitter. this utility allows the creation of programs that can be booted through the adsp- 21msp58/59 hip, in a similar fashion as eprom-bootable programs generated by the prom splitter utility. bus request and bus grant the ADSP-21MSP58/59 can relinquish control of the data and address buses to an external device. when the external device requires access to memory, it asserts the bus request signal ( br ). if the ADSP-21MSP58/59 is not performing an external memory access, it responds to the active br input in the follow- ing processor cycle by ? three-stating the data and address buses and the pms , dms , bms , rd , and wr output drivers, ? asserting the bus grant ( bg ) signal, and ? halting program execution. if gomode is enabled, the ADSP-21MSP58/59 will not halt pro- gram execution until it encounters an instruction that requires an external memory access. if the ADSP-21MSP58/59 is performing an external memory ac- cess when the external device asserts the br signal, then it will not three-state the memory interfaces or assert the bg signal until the cycle after the access is completed, which can be up to eight cycles later depending on the number of wait states. the instruction does not need to be completed when the bus is granted. if a single instruction requires two external memory accesses, the bus will be granted between the two accesses. when the br signal is released, the processor releases the bg signal, which reenables the output drivers, and continues pro- gram execution from the point where it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. low power operation the ADSP-21MSP58/59 has three low power modes that signifi- cantly reduce the power dissipation when the device operates under standby conditions. these modes are: ? powerdown ? idle ? slow idle the clkout pin may also be disabled to reduce external power dissipation. the clkout pin is controlled by bit 14 of sport0 autobuffer control register, dm[0x3ff3]. powerdown the ADSP-21MSP58/59 has a low power feature that lets the processors enter a very low power dormant state through hard- ware or software control. here is a brief list of powerdown fea- tures. refer to the adsp-2100 family users manual , chapter 9,
ADSP-21MSP58/59 rev. 0 C9C system interface for detailed information about the power- down feature. ? powerdown mode holds the processor in cmos standby with a maximum current of less than 100 m a in some modes. ? quick recovery from powerdown. in some modes, the proces- sor can begin executing instructions in less than 100 clkin cycles. ? support for an externally generated ttl or cmos processor clock. the external clock can continue running during powerdown without affecting the lowest power rating and 100 clkin cycle recovery. ? support for crystal operation includes disabling the oscillator to save power (the processor automatically waits 4096 clkin cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 100 clkin cycle start-up. ? powerdown is initiated by either the powerdown pin ( pwd ) or the software powerdown force bit. ? interrupt support allows an unlimited number of instructions to be executed before optionally powering down. the power- down interrupt also can be used as a non-maskable, edge- sensitive interrupt. ? context clear/save control lets the processor continue where it left off or start with a clean context when leaving the power- down state. ? the reset pin also can be used to terminate powerdown, and the host software reset feature can be used to terminate powerdown under certain conditions. ? setting the clkodis bit (bit 14 of the sport0 autobuffer control register [0x3ff3]) disables the clkout pin during powerdown. idle when the ADSP-21MSP58/59 is in the idle mode, the processor waits indefinitely in a low power state until an interrupt occurs. when an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the idle instruction. slow idle the idle instruction is enhanced on the ADSP-21MSP58/59 to let the processors internal clock signal be slowed, further reduc- ing power consumption. the reduced clock frequency, a pro- grammable fraction of the normal clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is idle (n); where n = 16, 32, 64, or 128. this instruction keeps the proces- sor fully functional, but operating at the slower clock rate. while it is in this state, the processors other internal clock signals, such as sclk, and timer clock, are reduced by the same ratio. clkout remains at the normal rate; it is not reduced. the de- fault form of the instruction, when no clock divisor is given, is the standard idle instruction. when the idle (n) instruction is used, it effectively slows down the processors internal clock and thus its response time to in- coming interruptsCCthe 1-cycle response time of the standard idle state is increased by n, the clock divisor. when an enabled interrupt is received, the ADSP-21MSP58/59 remains in the idle state for up to a maximum of n processor cycles ( n = 16, 32, 64, or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processors reduced internal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). standalone rom execution (adsp-21msp59 only) when the mmap and bmode pins both are set to 1, the rom is automatically enabled and execution commences from program memory location 0x0800 at the start of rom. this feature lets an embedded design operate without external memory components. to operate in this mode, the rom coded program must copy an interrupt vector table to the appropriate locations in program memory ram. in this mode, the rom enable bit defaults to 1 during reset. table iii. boot summary table bmode = 0 bmode = 1 mmap = 0 boot from eprom, boot from hip, then then execution starts execution starts at at internal ram internal ram location location 0x0000 0x0000 mmap = 1 no booting, execution stand alone mode, starts at external memory execution starts at location 0x0000 internal rom location 0x0800 ordering procedure for adsp-21msp59 rom processors to place an order for a custom rom-coded adsp-21msp59 processor, you must: 1. complete the following forms contained in the adsp rom ordering package , available from your analog devices sales representative: adsp-21msp59 rom specification form rom release agreement rom nre agreement & minimum quantity order (mqo) acceptance agreement for preproduction rom products 2. return the forms to analog devices along with two copies of the memory image file (.exe file) of your rom code. the files must be supplied on two 3.5" or 5.25" floppy disks for the ibm pc (dos 2.01 or higher). 3. place a purchase order with analog devices for nonrecurring engineering changes (nre) associated with rom product development. after this information is received, it is entered into analog devices rom manager system that assigns a custom rom model number to the product. this model number will be branded on all prototype and production units manufactured to these specifications. to minimize the risk of code being altered during this process, analog devices verifies that the .exe files on both floppy disks are identical, and recalculates the checksums for the .exe file entered into the rom manager system. the checksum data, in the form of a rom memory map, a hard copy of the .exe file, and a rom data verification form are returned to you for inspection.
rev. 0 C10C ADSP-21MSP58/59 a signed rom verification form and a purchase order for pro- duction units are required prior to any product being manufac- tured. prototype units may be applied toward the minimum order quantity. upon completion of prototype manufacture, analog devices will ship prototype units and a delivery schedule update for pro- duction units. an invoice against your purchase order for the nre charges is issued at this time. there is a charge for each rom mask generated and a mini- mum order quantity. consult your sales representative for de- tails. a separate order must be placed for parts of a specific package type, temperature range, and speed grade. analog interface the analog interface contains encoding circuitry (adc), decod- ing circuitry (dac), and processor interface logic. a block dia- gram of the ADSP-21MSP58/59 analog section is shown in figure 8. the analog interface is configured through the analog control register and the analog autobuffer/powerdown register (refer to ADSP-21MSP58/59 registers). the analog control regis- ter dm[0x3fee] configures the programmable gain stages, the analog input multiplexer, and the analog interface powerdown state. note that the unused bits must be cleared to zero. 16 output differential amp vin norm vin aux decouple ref_filter v ref vout p vout n mux dac pga analog smoothing filter buf voltage reference adc pga 16-bit sigma- delta dac 16-bit sigma- delta adc processor interface figure 8. analog interface block diagram a/d conversion the a/d conversion circuitry of the analog interface consists of an analog multiplexer, a programmable gain amplifier (adc pga), and a 16-bit sigma-delta analog-to-digital converter (adc). analog input multiplexer and amplifiers the analog multiplexer selects either the norm or aux input to the adcs sigma-delta modulator. the inputs should be ac coupled. the adc pga may be used to additionally increase the signal level by +6 db, +20 db, or +26 db. this gain is selected by bit 9 and bit 0 (ig0, ig1) of the analog control register. input sig- nal level to the sigma-delta adc should not exceed the v inmax specification. analog-to-digital converter the analog interfaces analog-to-digital converter consists of a 4th-order analog sigma-delta modulator, an anti-aliasing deci- mation filter, and an optional digital high-pass filter. for a detailed description of the adc components, refer to the adsp-2100 family users manual , chapter 8, analog interface. bit 10 of the analog control register (0x3fee) may be set to add an offset to the input of the adc sigma-delta converter. this offset moves adc sigma-delta idle tones out of the 4.0 khz speech band range. this added offset must be removed by the adc high-pass filter. therefore, the high-pass filter must be inserted when you use the offset feature. d/a conversion the d/a conversion circuitry of the analog interface consists of a sigma-delta digital-to-analog converter (dac), an analog smoothing filter, a programmable gain amplifier (dac pga), and a differential output amplifier. digital-to-analog converter the digital-to-analog converter consists of an optional digital high-pass filter, an anti-imaging interpolation filter, and a sigma-delta modulator. the digital filters and the sigma-delta modulator have the same characteristics as the filters and modulator of the adc. for detailed description of the dac components, refer to the adsp-2100 family users manual , chapter 8, analog interface. analog smoothing filter and programmable gain amplifier the analog smoothing filter consists of a 3rd-order switched ca- pacitor filter with a 3 db point at approximately 25 khz. the dacs programmable gain amplifier (dac pga) can be used to adjust the output signal level by C15 db to +6 db in 3 db increments. this gain is selected by bits 2C4 (og0, og1, og2) of the analog control register. differential output amplifier the analog output signal (vout p , vout n ) is produced by a differential amplifier. the differential amplifier meets specifica- tions for loads greater than 2 k w and has a maximum differen- tial output swing of 3.156 v peak-to-peak (3.17 dbm0). the dac will drive loads smaller than 2 k w , but with degraded performance. the output signal is dc-biased to the on-chip voltage reference (v ref ) and can be ac-coupled directly to a load or dc-coupled to an external amplifier. the vout p , vout n output must be used as a differential sig- nal otherwise performance will be severely compromised. do not use either pin as a single-ended output. operating the analog interface the analog interface is operated with several memory-mapped control and data registers. the adc and dac i/o data is re- ceived and transmitted through two memory-mapped data regis- ters. the data can also be autobuffered directly into (or from) on-chip memory. in both cases, the i/o processing is interrupt driven; two interrupts are dedicated to the analog interface, one for the adc receive data and one for the dac transmit data. the ADSP-21MSP58/59 must have an input clock frequency of 13 mhz. at this frequency, analog-to-digital and digital-to-ana- log converted data is transmitted at an 8 khz rate with a single 16-bit word transmitted every 125 m s. for detailed information about the analog interface, refer to the adsp-2100 family users manual , chapter 8, analog interface.
ADSP-21MSP58/59 rev. 0 C11C autobuffering in some applications, it is advantageous to perform block data transfers between the analog converters and processor memory. analog interface autobuffering enables the automatic transfer of data blocks directly from the adc to on-chip processor data memory or from on-chip processor data memory directly to the dac. adc and dac interrupts the analog interface generates two interrupts that signal either: (1) a 16-bit, 8 khz analog-to-digital or digital-to-analog conver- sion has been completed, or (2) an autobuffer block transfer has been completed (i.e., the data buffer contents have been received or transferred). when an analog interrupt occurs, the processor vectors to the addresses listed in table ii, interrupt priority & interrupt vector addresses . the adc receive and dac transmit interrupts occur at an 8 khz rate, indicating when the data registers should be ac- cessed. on the receive side, the adc interrupt is generated each time an a/d conversion cycle is completed and the 16-bit data word is available in the adc receive register. on the transmit side, the dac interrupt is generated each time an d/a conver- sion cycle is completed and the dac transmit register is ready for the next 16-bit data word. both interrupts are generated simultaneously at an 8 khz rate, occurring every 3250 instruction cycles with a 13 mhz internal processor clock. the interrupts are generated continuously, starting when the analog interface is powered up by setting the apwd bits (bits 5 and 6) to one in the analog control register. because both interrupts occur simultaneously, only one should be enabled (in imask) to vector to a single service routine that handles transmit and receive data. however, when using autobuffer transfers, both interrupts should be enabled. ADSP-21MSP58/59 registers figure 9 summarizes the ADSP-21MSP58/59 registers. some registers store values. for example, ax0 stores an alu oper- and; i4 stores a dag2 pointer. other registers consist of control bits and fields, or status flags. for example astat contains status flags from arithmetic operations, and fields in dwait control the number of wait states for different zones of data memory. a secondary set of registers in all computational units allows a single-cycle context switch. the bit and field definitions for control and status registers are given in the rest of this section, except imask, icntl, and ifc, which are defined earlier in this data sheet. the system control register, dwait register, timer registers, hip control registers, hip data registers, and sport control registers are all mapped into data memory locations; that is, you access these registers by reading and writing data memory locations rather than register names. the particular data memory address is shown with each memory-mapped register. register bit values shown on the following pages are the default bit values after reset. if no values are shown, the bits are indeter- minate at reset. reserved bits are shown in gray; these bits should always be written with zeros. powerdown control logic tx1 rx1 0x3ff2-0x3fef control registers sport 1 mx0 mx1 my0 my1 mr0 mr1 mr2 mf mac ax0 ax1 ay0 ay1 af ar alu s i se sb shifter sr1 sr0 dac adc control registers analog interface 0x3fec 0x3fed 0x3fee-0x3fef 0x3ffd 0x3ffc 0x3ffb tperiod tcount tscale timer i0 i1 i2 i3 m0 m1 m2 m3 l0 l1 l2 l3 dag 1 0x3fff 0x3ffe system control dm wait control program rom 4k x 24 adsp-21msp59 only data sram 2k x 16 0x3fe0-0x3fe5 0x3fe6-0x3fe7 0x3fe8 data status hmask host interface port dmd bus 16 24 14 14 pmd bus dma bus pma bus i4 i5 i6 i7 m4 m5 m6 m7 l4 l5 l6 l7 dag 2 sstat count stack 4 x 14 owrcntr cntr imask mstat astat status stack 12 x 25 loop stack 4 x 18 pc stack 16 x 14 program sequencer icntl ifc program sram 2k x 24 px flag tx0 rx0 0x3ffa-0x3ff3 control registers sport 0 figure 9. ADSP-21MSP58/59 registers
rev. 0 C12C ADSP-21MSP58/59 00000100001 11 1 1 1 1514131211109876543210 system control register 0x3fff sport0 enable 1 = enabled, 0 = disabled sport1 enable 1 = enabled, 0 = disabled sport1 configure 1 = serial port 0 = fi, fo, irq0 , irq1 , sclk bforce boot force bit bpage boot page select bwait boot wait states pwait program memory wait states az alu result zero an alu result negative av alu overflow ac alu carry as alu x input sign aq alu quotient mv mac overflow ss shifter input sign 76543210 00000000 astat pc stack empty pc stack overflow count stack empty count stack overflow status stack empty status stack overflow loop stack empty loop stack overflow 76543210 01010101 sstat (read -only) data register bank select 0 = primary, 1 = secondary bit reverse mode enable (dag1) alu overflow latch mode enable ar saturation mode enable mac result placement 0 = fractional, 1 = integer timer enable go mode enable 6543210 0000000 mstat tperiod period register 1514131211109876543210 tcount counter register 00000000 tcount scaling register 0x3ffd 0x3ffc 0x3ffb timer registers control registers
ADSP-21MSP58/59 rev. 0 C13C 00000000000 00 0 0 0 1514131211109876543210 sport0 control register 0x3ff6 multichannel enable mce internal serial clock generation isclk receive frame sync required rfsr receive frame sync width rfsw multichannel frame delay mfd only if multichannel mode enabled transmit frame sync required tfsr transmit frame sync width tfsw itfs internal transmit frame sync enable (or mcl multichannel length; 1 = 32 words, 0 = 24 words only if multichannel mode enabled ) slen serial word length dtype data format 00 = right justify, zero-fill unused msbs 01 = right justify, sign extend into unused msbs 10 = compand using ?law 11 = compand using a-law invrfs invert receive frame sync invtfs invert transmit frame sync (or invtdv invert transmit data valid only if multichannel mode enabled ) irfs internal receive frame sync enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sport0 multichannel receive word enable registers 1 = channel enabled 0 = channel ignored 0x3ffa 0x3ff9 0x3ff8 0x3ff7 sport0 multichannel transmit word enable registers 1 = channel enabled 0 = channel ignored 00000001111 11 1 1 1 1514131211109876543210 rom enable/data memory wait state control register 0x3ffe dwait4 dwait3 dwait2 dwait1 dwait0 rom enable (adsp-21msp59) 1 = enable 0 = disable control registers
rev. 0 C14C ADSP-21MSP58/59 0000 0 0 1514131211109876543210 sport0 autobuffer control register 0x3ff3 clkodis clkout disable control bit biasrnd mac biased rounding control bit tireg transmit autobuffer i register rbuf receive autobuffering enable tbuf transmit autobuffering enable rmreg receive autobuffer m register rireg receive autobuffer i register tmreg transmit autobuffer m register 1514131211109876543210 sport0 sclkdiv serial clock divide modulus 0x3ff5 1514131211109876543210 0000000000 00 0 0 0 sport1 control register 0x3ff2 flag out (read only) internal serial clock generation isclk receive frame sync required rfsr receive frame sync width rfsw transmit frame sync required tfsr transmit frame sync width tfsw itfs internal transmit frame sync enable slen serial word length dtype data format 00 = right justify, zero-fill unused msbs 01 = right justify, sign extend into unused msbs 10 = compand using ?law 11 = compand using a-law invrfs invert receive frame sync invtfs invert transmit frame sync irfs internal receive frame sync enable 1514131211109876543210 sport0 rfsdiv receive frame sync divide modulus 0x3ff4 control registers
ADSP-21MSP58/59 rev. 0 C15C 00000000000 00 0 0 0 1514131211109876543210 hmask register 0x3fe8 host hdr5 read host hdr4 read host hdr3 read host hdr2 read host hdr1 read host hdr0 read host hdr0 write host hdr1 write host hdr2 write host hdr3 write host hdr4 write host hdr5 write interrupt enables 1 = enable 0 = disable 0000 0 0 1514131211109876543210 analog autobuffer/powerdown control register 0x3fef xtaldis xtal pin disable during powerdown 1 = disabled, 0 = enabled (xtal pin should be disabled when no external crystal is connected) xtaldelay delay startup from powerdown 4096 cycles 1 = delay, 0 = no delay (use delay to let internal phase locked loop or external oscillator stabilize) pdforce powerdown force 1 = force processor to vector to powerdown interrupt pucr powerup context reset 1 = soft reset, 0 = resume execution arbuf adc receive autobuffer enable atbuf dac transmit autobuffer enable armreg receive m register arireg receive i register atmreg transmit m register atireg transmit i register 1514131211109876543210 sport1 sclkdiv serial clock divide modulus 0x3ff1 1514131211109876543210 sport1 rfsdiv receive frame sync divide modulus 0x3ff0 control registers
rev. 0 C16C ADSP-21MSP58/59 00000000000 00 0 0 0 1514131211109876543210 analog control register 0x3fee adc offset ig0 adc input gain daby dac high pass filter bypass 1 = bypass, 0 = insert adby adc high pass filter bypass 1 = bypass, 0 = insert apwd analog interface powerdown 0 = powerdown, 1 = enable (set both bits to 1 to enable analog interface) ig1 adc input gain ims adc input multiplexer select 1 = aux input, 0 = norm input og2, og1, og0 dac output gain (for pga) og2 og1 og0 0db +6db +20db +26db ig1 0 0 1 1 ig0 0 1 0 1 gain +6db +3db 0db ?db ?db ?db ?2db ?5db ig2 0 0 0 0 1 1 1 1 ig1 0 0 1 1 0 0 1 1 ig1 0 1 0 1 0 1 0 1 gain ig0, ig1 adc input gain (for pga) all bits are set to 0 at processor reset. (reserved bits 11?5 must always be set to 0) 1514131211109876543210 dm(0x3fed) adc receive 1514131211109876543210 dm(0x3fec) dac transmit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x3fe5 hip data registers hdr5 0x3fe4 0x3fe3 0x3fe2 0x3fe1 0x3fe0 hdr4 hdr3 hdr2 hdr1 hdr0 control registers
ADSP-21MSP58/59 rev. 0 C17C 00000000100 00 0 0 0 1514131211109876543210 hsr7 0x3fe7 ADSP-21MSP58/59 hdr0 write ADSP-21MSP58/59 hdr1 write ADSP-21MSP58/59 hdr2 write ADSP-21MSP58/59 hdr3 write ADSP-21MSP58/59 hdr4 write ADSP-21MSP58/59 hdr5 write overwrite mode software reset 00000000000 00 0 0 0 1514131211109876543210 hsr6 0x3fe6 ADSP-21MSP58/59 hdr5 write ADSP-21MSP58/59 hdr4 write ADSP-21MSP58/59 hdr3 write ADSP-21MSP58/59 hdr2 write ADSP-21MSP58/59 hdr1 write ADSP-21MSP58/59 hdr0 write host hdr0 write host hdr1 write host hdr2 write host hdr3 write host hdr4 write host hdr5 write control registers ADSP-21MSP58/59 extended instruction set the ADSP-21MSP58/59 has a number of additional instruc- tions beyond the standard adsp-2100 family instruction set. these additional instructions and mathematical operations are described below. slow idle slow idle allows slowing the processors internal clock by a factor of 16, 32, 64, or 128 during idle. the instruction source code is specified as follows: syntax: idle (n); permissible values for n 16, 32, 64, 128 examples: idle; idle (16); description: the idle instruction causes the processor to wait indefinitely in a low power state until an in- terrupt occurs. when an unmasked interrupt oc- curs, it is serviced; execution then continues with the instruction following the idle instruction. the optional value provides a slow idle fea- ture; slowing the clock down by the factor set with the value. interrupt enable and disable instructions the ADSP-21MSP58/59 supports an interrupt enable instruc- tion and interrupt disable instruction. interrupts are enabled by default at reset. the interrupt enable instruction source code is specified as follows: instruction set description the ADSP-21MSP58/59 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. the assembly language, which takes full advantage of the processors unique architecture, offers the following benefits: ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction assembles into a single 24-bit word and executes in a single cycle. ?the syntax is a superset of the adsp-2100 family assembly language and is completely source and object code compatible with other family members. programs may, however, need to be relocated to utilize internal memory and conform to the ADSP-21MSP58/59 interrupt vector and reset vector map. ? sixteen condition codes are available. for conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. ? multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches and one write to processor memory space during a single instruction cycle. consult the adsp-2100 family users manual for a complete description of the syntax and an instruction set reference.
rev. 0 C18C ADSP-21MSP58/59 syntax: ena ints; description: executing the ena ints instruction allows all unmasked interrupts to be serviced again. the interrupt disable instruction source code is specified as follows: syntax: dis ints; description: reset enables interrupt servicing. executing the dis ints instruction causes all interrupts to be masked without changing the contents of the imask register. disabling interrupts does not affect the autobuffer circuitry, which will operate normally whether or not interrupts are enabled. the disable interrupt instruction masks all user interrupts including the powerdown interrupt. extended alu and multiplier operations the following extended computation operations are available only on the ADSP-21MSP58/59 processor. the term base in- struction set refers to the computations and instructions avail- able on all adsp-21xx processors. additional constants for alu operations a new set of numerical constants may be used in all nonmulti- function alu operations (except divs and divq) using both x and y operands. the instruction source code is specified as follows: syntax: [if condition] ? ar ? = xop function ? yop ? ? af ?? constant ? permissible xops ax0, ax1, ar, mr0, mr1, mr2, sr0, sr1 permissible functions add/add with carry, subtract xCy/subtract xC y with borrow, subtract yCx/subtract yCx with borrow, and, or, xor permissible yops (base instruction set) ay0, ay1, af permissible yops and constants (extended instruction set) ay0, ay1, af, 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767, C2, C3, C5, C9, C17, C33, C65, C129, C257, C513, C1025, C2049, C4097, C8193, C16385, C32768 examples: ar = ar+1; ar = mr1 - 33; if gt af = ax1 or 16; description: test the optional condition and, if true, perform the specified function. if false then perform a no- operation. omitting the condition performs the function unconditionally. the operands are con- tained in the data registers specified in the in- struction or optionally a constant may be used. additional constants for alu pass operation a new set of numerical constants may be used in the pass in- struction. the instruction source code is specified as follows: syntax: [if condition] ? ar ? = pass ? yop ? ? af ?? constant ? permissible yops (base instruction set) ay0, ay1, af permissible yops and constants (extended instruction set) ay0, ay1, af, 0, 1, 2, 3, 4, 5, 7, 8, 9, 15, 16, 17, 31, 32, 33, 63, 64, 65, 127, 128, 129, 255, 256, 257, 511, 512, 513, 1023, 1024, 1025, 2047, 2048, 2049, 4095, 4096, 4097, 8191, 8192, 8193, 16383, 16384, 16385, 32766, 32767, C1, C2, C3, C4, C5, C6, C8, C9, C10, C16, C17, C18, C32, C33, C34, C64, C65, C66, C128, C129, C130, C256, C257, C258, C512, C513, C514, C1024, C1025, C1026, C2048, C2049, C2050, C4096, C4097, C4098, C8192, C8193, C8194, C16384, C16385, C16386, C32767, C32768 examples: if ge ar = pass ay0; if eq af = pass C1025; description: test the optional condition and, if true, pass the source operand unmodified through the alu block and store in the destination location. if the condition is not true, perform a no-operation. omitting the condition performs the pass uncon- ditionally. the source operand is contained in the data registers specified in the instruction or optional constant. the pass instruction performs the transfer to the ar register and affect the status flag; this instruc- tion is differ ent from a register move operation which does not affect any status flags. pass 0 is one method of clearing ar. pass 0 can also be combined in a multifunction instruction in con- junction with memory reads and writes to clear ar. note: the alu status flags (in the astat register) are not defined for the execution of this instruc- tion when using the constant values other than 0, 1, and C1. alu bit operations the additional constants for alu operations allow you to code bit test, set, clear, and toggle operations through careful choice of the constant and alu function. for streamlined programming, the source code for these operations can also be specified as: syntax: [if condition] ? ar ? = ? tstbit n of xop; ? ? af ?? setbit n of xop; ? ? clbit n of xop; ? ? tgbit n of xop; ? permissible xops ax0, ax1, ar, mr0, mr1, mr2, sr0, sr1 permissible n values (0 = lsb ) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 examples: af=tstbit 5 of ar; if ne jump set; /* jump to set if bit is set */ definitions of operations tstbit is an and operation with a 1 in the selected bit setbit is an or operation with a 1 in the selected bit clbit is an and operation with a 0 in the selected bit tgbit is an xor operation with a 1 in the selected bit result-free alu operations the result-free alu operations allow the generation of condi- tion flags based on an alu operation but discard the result. the source code for the instruction is specified as follows: syntax: none = ; where is any unconditional alu operation of the 21xx base instruction set (except divs or divq). (note that the addi- tional constant alu operations of the adsp-2171/2181 ex- tended instruction set are not allowed.)
ADSP-21MSP58/59 rev. 0 C19C examples: none = ax0 C ay0; none = pass sr0; description: perform the designated alu operation, set the condition flags, then discard the result value. this allows the testing of register values without disturbing the ar or af register values. mac operations a modified mac operation allows additional type 9 instruc- tions. the conditional alu/mac instruction has been modi- fied to allow the x operand to be used as the y operand as well. this allows a single cycle x 2 , and also ? x 2 operations. the new mac instructions allow the use of any xop as both the x and y operands. the instructions source code is specified as follows: syntax: [if condition] ? mr ? = ? [mr +] ? xop * yop (uu); ? mf ?? [mr C] ? xop (ss) ; (rnd); permissible xops ar, mr0, mr1, mr2, mx0, mx1, sr0, sr1 example: if lt mr=mr+ sr0 * sr0 (ss); note: both x operators must be the same register. biased rounding a new mode has been added to allow biased rounding in addi- tion to the normal unbiased rounding. when the biasrnd bit is set to 0 the normal unbiased rounding operations occur. when the biasrnd bit is set to 1, biased rounding occurs in- stead of the normal unbiased rounding. when operating in bi- ased rounding mode all rounding operations with mr0 set to 0x8000 will round up, rather than only rounding odd mr1 values up. for example: mr value before rnd biased rnd result unbiased rnd re sult 00-0000-8000 00-0001-8000 00-0000-8000 00-0001-8000 00-0002-8000 00-0002-8000 00-0000-8001 00-0001-8001 00-0001-8001 00-0001-8001 00-0002-8001 00-0002-8001 00-0000-7fff 00-0000-7fff 00-0000-7fff 00-0001-7fff 00-0001-7fff 00-0001-7fff this mode only has an effect when the mr0 register contains 0x8000, all other rounding operation work normally. this mode was added to allow more efficient implementation of bit speci- fied algorithms which specify biased rounding such as the gsm speech compression routines. unbiased rounding is preferred for most algorithms. note: biasrnd bit is bit twelve of the sport0 autobuffer control register. interrupt enable the ADSP-21MSP58/59 supports an interrupt enable instruc- tion. interrupts are enabled by default at reset. the instruction source code is specified as follows: syntax: ena ints; description: executing the ena ints instruction allows all unmasked interrupts to be serviced again. interrupt disable the ADSP-21MSP58/59 supports an interrupt disable instruc- tion. the instruction source code is specified as follows: syntax: dis ints; description: reset enables interrupt servicing. executing the dis ints instruction causes all interrupts to be masked without changing the contents of the imask register. disabling interrupts does not af- fect the autobuffer circuitry, which will operate normally whether or not interrupts are enabled. the disable interrupt instruction masks all user interrupts including the powerdown interrupt. circuit design considerations the following sections discuss interfacing analog signals to the ADSP-21MSP58/59. analog signal input figure 10 shows the recommended input circuit for the analog in- put pin (either vin norm or vin aux ). the circuit of figure 10 implements a first-order low-pass filter (r1c1) with a 3 db point less than 40 khz. this is the only filter required external to the processor to prevent aliasing of the sampled signal. since the ADSP-21MSP58/59s sigma-delta adc uses a highly oversampled approach that transfers the bulk of the anti-aliasing filtering into the digital domain, the off-chip anti-aliasing need only be of low order. vin norm vin aux decouple pga c3 c2 c1 r1 input source star ground ADSP-21MSP58/59 mux figure 10. recommend analog input circuit the on-chip adc pga can be used when there is not enough gain in the input circuit. the pga gain is set by bits 9 and 0 (ig1, ig0) of the processors analog control register. the gain must be chosen to ensure that a full-scale input signal (at r1 in figure 10) produces a signal level at the input to the sigma-delta modulator of the adc that does not exceed vin max (refer to the analog interface electrical characteristics specifications). vin norm and vin aux are biased at the internal reference volt- age (nominal of 2.5 v) of the ADSP-21MSP58/59, which lets the analog section of the processor operate from a single supply. the input signal should be ac-coupled with an external capaci- tor (c2). the value of c2 is determined by the input resistance of the analog input (vin norm , vin aux ) (200 k w ) and the de- sired cutoff frequency. the cutoff frequency should be 30 hz. the following equation should be used to determine the values of r1, c1, and c2; r1 should be 2.2 k w . c2 should be 3 0.027 m f; c3 should be equal to c2. c 2 = 1 2 p f 1 r in r in = ADSP-21MSP58/59 input resistance (200 k w ) f 1 = cutoff frequency <30 hz r 1 = 1 2 p f 2 c 1 r 1 2.2 k w f 2 > 20 khz < 40 khz * c 1 = 1 2 p f 2 r 1 for optimum adc performance, c1 should be an npo type capacitor. *if minimum (<0.1 db) rolloff at 4 khz is desired, f 2 should be set to 40 khz.
rev. 0 C20C ADSP-21MSP58/59 application examples the ADSP-21MSP58/59 is ideal for speech processing applica- tions where high performance for analog and digital circuitry is required, but board space is severely limited. the cellular radio handset is one application. here the ADSP-21MSP58/59 can digitize the speech, then perform compression algorithms that sufficiently reduce the bit rate for transmission in a limited radio bandwidth. definition of specifications absolute gain absolute gain is a measure of converter gain for a known signal. absolute gain is measured with a 1.0 khz sine wave at 0 dbm0. the absolute gain specification is used as a reference for the gain tracking error specification. gain tracking error gain tracking error measures changes in converter output for different signal levels relative to an absolute signal level. the absolute signal level is 1.0 khz at 0 dbm0. gain tracking error at 0 dbm0 is 0 db by definition. snr + thd signal-to-noise ratio plus total harmonic distortion is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components in the frequency range 300 hzC3400 hz, including harmonics but excluding dc. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those which neither m nor n are equal to zero. the second order terms in- clude (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb), and (fa C 2fb). idle channel noise idle channel noise is defined as the total signal energy measured at the output of the device when the input is grounded (mea- sured in the frequency range 300 hzC3400 hz). crosstalk crosstalk is defined as the ratio of the rms value of a full-scale signal appearing on one channel to the rms value of the same signal that couples onto the adjacent channel. crosstalk is ex- pressed in db. power supply rejection power supply rejection measures the susceptibility of a device to a signal on the power supply. power supply rejection is mea- sured by modulating a signal on the power supply and measur- ing the signal at the output (relative to 0 db). power supply rejection is defined as the ratio of the rms value of the modula- tion signal to the rms value of the same signal in the adc/dac channel. group delay group delay is defined as the derivative of radian phase with re- spect to radian frequency, ?f ( w )/ ?w . group delay is a measure of the average delay of a system as a function of frequency. a linear system with a constant group delay has a linear phase re- sponse. the deviation of group delay away from a constant indi- cates the degree of nonlinear phase response of the system. analog signal output the differential analog output (vout p , vout n ) is produced by an on-chip differential amplifier which is part of the processors analog interface. the differential amplifier will meet dynamic specifications for loads greater than 2 k w (r l 3 2 k w ) and has a maximum differential output voltage swing of 3.156 v peak-to- peak (3.17 dbm0). the dac will drive loads smaller than 2 k w , but with degraded dynamic performance. the differential out- put can be ac-coupled directly to a load or dc-coupled to an ex- ternal amplifier. figure 11 shows a simple circuit providing a differential output with ac coupling. the capacitor of this circuit (c out ) is op- tional; if used, its value can be chosen as follows: c out = 1 (60 p ) r l vout p vout n c out c out r l ADSP-21MSP58/59 figure 11. example circuit for differential output with ac coupling the vout p and vout n outputs must be used as differential outputs (do not use either as a single-ended output). figure 12 shows an example circuit which can be used to convert the dif- ferential output to a single-ended output. the circuit uses a dif- ferential -to-single-ended amplifier, the analog devices ssm2141. ADSP-21MSP58/59 5 7 4 1 gnd a 0.1? gnd a ssm2141 ?2v 0.1? gnd a +12v vout p vout n v out figure 12. example circuit for single-ended output voltage reference filter capacitance figure 13 shows the recommended reference filter capacitor connections. the capacitor grounds should be connected to the same star ground point shown in figure 10. voltage reference 0.1? star ground ADSP-21MSP58/59 10? ref_filter v ref buf figure 13. voltage reference filter capacitor
ADSP-21MSP58/59Cspecifications recommended operating conditions b grade parameter min max unit v dd supply voltage 4.50 5.50 v t amb ambient operating temperature C40 +85 c see environmental conditions for information on thermal specifications. electrical characteristics parameter test conditions min max unit v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 4, 5 @ v dd = min, i oh = C0.5 ma 2.4 v @ v dd = min, i oh = C100 m a 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min, i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max, v in = v dd max 10 m a i il lo-level input current 3 @ v dd = max, v in = 0 v 10 m a i ozh tristate leakage current 7 @ v dd = max, v in = v dd max 8 10 m a i ozl tristate leakage current 7 @ v dd = max, v in = 0 v 8 10 m a i dd digital supply current (idle) 6, 9 @ v dd = max, codec inactive 18 ma i dd digital supply current (dynamic) 9, 10 @ v dd = max, v cc = max 92 ma i dd digital supply current (powerdown) 9 @ v dd = max, see adsp-2100 family users manual, chapter 9 100 m a i cc analog supply current (dynamic) 9 codec active 18 ma c i input pin capacitance 3, 11, 12 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 7, 11, 12 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 bidirectional pins: d0-d23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, hd0-hd7/had0-had7. 2 input only pins: reset , irq2 , br , mmap, dr0, dr1, hsel , hsize, bmode, hmd0, hmd1, hrd /hwr, hwr / hds , pwd , ha2/ale, ha1-0. 3 input only pins: clkin, reset , irq2 , br , mmap, dr0, dr1, hsel , hsize, bmode, hmd0, hmd1, hrd /hwr, hwr / hds , pwd , ha2/ale, ha1-0. 4 output pins: bg , pms , dms , bms , rd , wr , a0-a13, dt0, dt1, clkout, hack , fl0. 5 although specified for ttl outputs, all ADSP-21MSP58/59 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 6 idle refers to ADSP-21MSP58/59 state of operation during idle instruction. deasserted pins are driven to either v dd or gnd. refer to chart in back for lower idle currents. 7 three-statable pins: a0-a13, d0-d23, pms , dms , bms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rsf1, hd0-hd7/had0-had7. 8 0 v on br, clkin active (to force three-state condition). 9 current reflects the digital portion of device operating with no output loads and a 2 k w load on the analog output (vout p , vout n ). 10 t ck = 76.92 ns, codec active, 80% execution type 1 instructions, with random data. for typical figures for digital and analog supply currents, refer to power dissipation section. 11 guaranteed but not tested. 12 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. C21C rev. 0 ADSP-21MSP58/59
rev. 0 C22C ADSP-21MSP58/59 memory requirements this chart links common memory device specification names and ADSP-21MSP58/59 timing parameters for your convenience. common parameter memory device name function specification name t asw a0-a13, dms , pms address setup to setup before wr low write start t aw a0-a13, dms , pms setup address setup before wr deasserted to write end t wra a0-a13, dms , pms address hold time hold after wr deasserted t dw data setup before wr high data setup time t dh data hold after wr high data hold time t rdd rd low to data valid oe to data valid t aa a0-a13, dms , pms , address access time bms to data valid esd sensitivity the ADSP-21MSP58/59 is an esd (electrostatic discharge) sensitive device. electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. permanent damage may occur to devices subjected to high energy electrostatic discharges. the ADSP-21MSP58/59 features proprietary esd protection circuitry to dissipate high energy discharges (human body model). proper esd precautions are recommended to avoid performance degradation or loss of function- ality. unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination before devices are removed. general notes use the exact timing information given. do not attempt to de- rive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an in- dividual device, the values given in this data sheet reflect statisti- cal variations and worst cases. consequently, you cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timing; it is dependent on the internal design. timing requirements apply to signals that are controlled outside the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates cor- rectly with another device. switching characteristics tell you what the device will do under a given circumstance. also, use the switching characteristics to ensure any timing requirement of a device connected to the processor (such as memory) is satisfied. timing parameters warning! esd sensitive device absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v input voltage . . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v output voltage swing . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range (ambient) . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADSP-21MSP58/59 rev. 0 C23C frequency response adc adc dac dac frequency max min max min (hz) (db) (db) (db) (db) 0+ C60.00 n/a C60.00 n/a 75 C25.00 n/a C25.00 n/a 150 +0.266 C0.134 +0.015 C0.185 300 +0.272 C0.128 +0.030 C0.170 1000 +0.000 +0.000 +0.000 +0.000 2000 +0.050 C0.350 +0.050 C0.200 3000 C0.200 C0.600 C0.050 C0.300 3400 C0.300 C0.700 C0.090 C0.340 3700 C0.375 C0.775 C0.120 C0.370 3850 C25.00 n/a C25.00 n/a 4000 C60.00 n/a C60.00 n/a notes all specifications relative to absolute gain @ 1.0 khz. adc and dac high-pass filters inserted . adc specifications do not include rc filter attenuation and assumes an ac coupled input (see analog test conditions for rc filter details). noise & distortion parameter min max unit test condition adc intermodulation distortion C60 db m, n = 1 and 2; f a = 984; f b = 1047 dac intermodulation distortion C70 db m, n = 1 and 2; f a = 984; f b = 1047 adc idle channel noise 65 dbm0 dac idle channel noise 72 dbm0 adc crosstalk 1 C65 db adc input signal level: 1.0 khz, 0 dbm0 dac input at idle. dac crosstalk 1 C65 db adc input signal level: analog ground dac output signal level: 1.0 khz, 0 dbm0 adc power supply rejection 1 C55 db input signal level at v cc and v dd pins: 1.0 khz, 100 mv p-p sine wave dac power supply rejection 1 C55 db input signal level at v cc and v dd pins: 1.0 khz, 100 mv p-p sine wave adc group delay 1 1 ms 300 hzC3000 hz dac group delay 1 1 ms 300 hzC3000 hz adc snr and thd 65 db 1.0 khz, 0 dbm0 dac snr and thd 72 db 1.0 khz, 0 dbm0 note 1 guaranteed but not tested. v in ?dbm0 100 80 0 snr + thd ?db ?0 10 ?0 ?0 ?0 ?0 ?0 0 60 40 20 dac snr + thd 3.17 peak @ 72db slope = 20db 20dbm0 v in ?dbm0 100 80 0 snr + thd ?db ?0 10 ?0 ?0 ?0 ?0 ?0 0 60 40 20 adc snr + thd 3.17 peak @ 65db slope = 20db 20dbm0 figure 14. snr + thd vs. v in
rev. 0 C24C ADSP-21MSP58/59 analog interface electrical characteristics symbol parameter min typ max unit adc r i input resistance 1, 2 at vin norm , vin aux 200 k w vin max maximum input range 1, 3 3.156 v p-p dac: r o output resistance 1, 4 2.5 w v ooff output dc offset 5 C400 400 mv v o maximum voltage output swing (p-p) across r l single-ended 1 3.156 v differential 1 6.312 v r l load resistance 1, 4 2k w reference buffer: voltage reference (v ref ) 2.25 2.75 v output impedence 1 250 w capacitive load 1 10 nf psrr 1 55 db notes test conditions for all analog interface tests: adc pga bypassed, dac pga set to 0 db gain, with 2 k w load on analog output (vout p , vout n ), v cc = 5.0 v. 1 guaranteed but not tested. 2 varies with pga setting. 3 at input to sigma-delta modulator of adc. 4 at vout p , vout n . 5 between vout p and vout n . gain parameter min typ max unit test conditions adc absolute gain C0.7 0 0.7 dbm0 1.0 khz, 0 dbm0 adc gain tracking error C0.1 0 0.1 dbm0 1.0 khz, +3 to C50 dbm0 adc pga relative gain C0.6 0 0.6 dbm0 1.0 khz dac absolute gain C0.75 0 0.75 dbm0 1.0 khz, 0 dbm0 dac gain tracking error C0.1 0 0.1 dbm0 1.0 khz, +3 to C50 dbm0 dac pga relative gain C0.6 0 0.6 dbm0 1.0 khz
ADSP-21MSP58/59 rev. 0 C25C parameter min max unit clock signals t ck is defined as 0.5 t cki. the ADSP-21MSP58/59 uses an input clock with a quency equal to half the instruction rate; a 13 mhz input clock (which is equivalent to 76.92 ns) yields a 38.46 ns processor cycle (equivalent to 26 mhz). t ck values within the range of 0.5 t cki period should be substituted for all relevant timing parameters to obtain specification value. example: t ckh = 0.5t ck C 7 ns = 0.5 (38.46 ns) C 7 ns = 12.23 ns. timing requirement: t cki clkin period 76.92 125 ns t ckil clkin width low 20 ns t ckih clkin width high 20 ns switching characteristic: t ckl clkout width low 0.5t ck C 7 ns t ckh clkout width high 0.5t ck C 7 ns t ckoh clkin high to clkout high 0 20 ns control signals timing requirement: t rsp reset width low 5t ck 1 ns notes 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable clkin (not including crystal oscillator start-up time). clkin t ckil t ckih t cki t ckoh t ckh t ckl clkout figure 15. clock signals
rev. 0 C26C ADSP-21MSP58/59 parameter min max unit interrupts and flags timing requirement: t ifs irqx or fi setup before clkout low 1, 2, 3 0.25t ck + 15 ns t ifh irqx or fi hold after clkout high 1, 2, 3 0.25t ck ns switching characteristics: t foh flag output hold after clkout low 4 0.5t ck C 7 ns t fod flag output delay from clkout low 4 0.5t ck + 5 ns notes 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (refer to interrupt controller operation in the program control chapter of the users manual for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 , irq1 , and irq2 . 4 flag output = fl0 and fo. flag outputs t fod t ifs t ifh clkout t foh irq fi x figure 16. interrupts and flags
ADSP-21MSP58/59 rev. 0 C27C parameter min max unit bus request/grant timing requirement: t bh br hold after clkout high 1 0.25t ck + 2 ns t bs br setup before clkout low 1 0.25t ck + 17 ns switching characteristic: t sd clkout high to dms , pms , bms , 0.25t ck + 10 ns rd , wr disable t sdb dms , pms , bms , rd , wr disable to bg low 0 ns t se bg high to dms , pms , bms , rd , wr enable 0 ns t sec dms , pms , bms , rd , wr enable to clkout high 0.25t ck C 7 ns notes 1 br is an asynchronous signal. if br meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. refer to the adsp-2100 family users manual for br / bg cycle relationships. clkout t bs t bh br clkout t sd t sdb t sec t se pms , dms , bms , rd , wr bg figure 17. bus requestCbus grant
rev. 0 C28C ADSP-21MSP58/59 parameter min max unit memory read timing requirement: t rdd rd low to data valid 0.5t ck C 11 + w ns t aa a0-a13, pms , dms , bms to data valid 0.75t ck C 12 + w ns t rdh data hold from rd high 0 ns switching characteristic: t rp rd pulse width 0.5t ck C 5 + w ns t crd clkout high to rd low 0.25t ck C 5 0.25t ck + 7 ns t asr a0-a13, pms , dms , bms setup before rd low 0.25t ck C 6 ns t rda a0-a13, pms , dms , bms hold after rd deasserted 0.25t ck C 3 ns t rwr rd high to rd or wr low 0.5t ck C 5 note w = wait states t ck . clkout t rp wr dms , pms , bms t rda t asr t crd t rwr t rdh t rod t aa a0 ?a13 rd d figure 18. memory read
ADSP-21MSP58/59 rev. 0 C29C parameter min max unit memory write switching characteristic: t dw data setup before wr high 0.5t ck C 7 + w ns t dh data hold after wr high 0.25t ck C 2 ns t wp wr pulse width 0.5t ck C 5 + w ns t wde wr low to data enabled 0 ns t asw a0-a13, dms , pms setup before wr low 0.25t ck C 6 ns t ddr data disable before wr or rd low 0.25t ck C 6 ns t cwr clkout high to wr low 0.25t ck C 5 0.25t ck + 7 ns t aw a0-a13, dms , pms , setup before wr deasserted 0.75t ck C 9 + w ns t wra a0-a13, dms , pms hold after wr deasserted 0.25t ck C 3 ns t wwr wr high to rd or wr low 0.5t ck C 5 ns note w = wait states t ck. clkout t wp dms , pms t wra t asw t cwr t wwr t wde a0 ?a13 wr d t aw t dh t ddr t dw rd figure 19. memory write
rev. 0 C30C ADSP-21MSP58/59 parameter min max unit serial ports timing requirement: t sck sclk period 50 ns t scs dr/tfs/rfs setup before sclk low 4 ns t sch dr/tfs/rfs hold after sclk low 7 ns t scp sclk in width 20 ns switching characteristic: t cc clkout high to sclk out 0.25t ck 0.25t ck + 10 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 15 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 15 ns t scdh dt hold after sclk high 0 ns t tde tfs(alt) to dt enable 0 ns t tdv tfs(alt) to dt valid 14 ns t scdd sclk high to dt disable 15 ns t rdv rfs (multichannel, frame delay zero) to dt valid 15 ns clkout t rh t rd t cc t cc t sch t scs t scp t scp t sck t scde t scdv t scdh t scdd t tdv t tde t rdv sclk dr rfs in tfs in rfs out tfs out dt tfs alternate frame mode rfs multichannel mode, frame delay 0 (mfd = 0) figure 20. serial ports
ADSP-21MSP58/59 rev. 0 C31C parameter min max unit host interface port separate data and address (hmd1 = 0) read strobe and write strobe (hmd0 = 0) timing requirement: t hsu ha2-0 setup before start of write or read 1, 2 5ns t hdsu data setup before end of write 3 5ns t hwdh data hold after end of write 3 3ns t hh ha2-0 hold after end of write or read 3, 4 3ns t hrwp read or write pulse width 5 20 ns switching characteristic: t hshk hack low after start of write or read 1, 2 015ns t hkh hack hold after end of write or read 3, 4 015ns t hde data enabled after start of read 2 0ns t hdd data valid after start of read 2 18 ns t hrdh data hold after end of read 4 0ns t hrdd data disabled after end of read 4 7ns notes 1 start of write = hwr low and hsel low. 2 start of read = hrd low and hsel low. 3 end of write = hwr high or hsel high. 4 end of read = hrd high or hsel high. 5 read pulse width = hrd low and hsel low, write pulse width = hwr low and hsel low. ha2? t hkh t hrwp t hh address t hsu data t hshk t hwdh t hdsu hsel hwr hack host write cycle hd7? ha2? t hkh t hrwp t hh address t hsu data t hshk t hrdh t hrdd hsel hrd hack host read cycle hd7? t hde t hdd figure 21. host interface port (hmd1 = 0, hmd0 = 0)
rev. 0 C32C ADSP-21MSP58/59 parameter min max unit host interface port separate data and address (hmd1 = 0) read strobe and write strobe (hmd0 = 1) timing requirement: t hsu ha2-0, hrw setup before start of write or read 1 5ns t hdsu data setup before end of write 2 5ns t hwdh data hold after end of write 2 3ns t hh ha2-0, hrw hold after end of write or read 2 3ns t hrwp read or write pulse width 3 20 ns switching characteristic: t hshk hack low after start of write or read 1 015 ns t hkh hack hold after end of write or read 2 015 ns t hde data enabled after start of read 1 0ns t hdd data valid after start of read 1 18 ns t hrdh data hold after end of read 2 0ns t hrdd data disabled after end of read 2 7ns notes 1 start of write or read = hds low and hsel low. 2 end of write or read = hds high and hsel high. 3 read or write pulse width = hds low and hsel low. ha2? t hkh t hrwp t hh address t hsu t hshk hsel hack host read cycle hd7? hds hrw data t hrdh t hrdd t hde t hdd ha2? t hkh t hrwp t hh address t hsu data t hshk t hwdh t hdsu hsel hack host write cycle hd7? hds hrw figure 22. host interface port (hmd1 = 0, hmd0 =1)
ADSP-21MSP58/59 rev. 0 C33C parameter min max unit host interface port multiplexed data and address (hmd1 = 1) read strobe and write strobe (hmd0 = 0) timing requirement: t halp ale pulse width 10 ns t hasu had15-0 address setup, before ale low 5 ns t hah had15-0 address hold after ale low 2 ns t hals start of write or read after ale low 1, 2 10 ns t hdsu had15-0 data setup before end of write 3 5ns t hwdh had15-0 data hold after end of write 3 3ns t hrwp read or write pulse width 5 20 ns switching characteristic: t hshk hack low after start of write or read 1, 2 015ns t hkh hack hold after end of write or read 3, 4 015ns t hde had15-0 data enabled after start of read 2 0ns t hdd had15-0 data valid after start of read 2 18 ns t hrdh had15-0 data hold after end of read 0 ns t hrdd had15-0 data disabled after end of read 4 7ns notes 1 start of write = hwr low and hsel low. 2 start of read = hrd low and hsel low. 3 end of write = hwr high or hsel high. 4 end of read = hrd high or hsel high. 5 read pulse width = hrd low and hsel low, write pulse width = hwr low and hsel low. t hkh ale t hrwp address t halp data t hshk t hwdh t hdsu hsel hack host write cycle had7? hwr t hals t hasu t hah t hkh ale t hrwp address t halp data t hshk t hrdh t hde hsel hack host read cycle had7? hrd t hals t hasu t hah t hrdd t hdd figure 23. host interface port (hmd1 = 1, hmd0 = 0)
rev. 0 C34C ADSP-21MSP58/59 parameter min max unit host interface port multiplexed data and address (hmd1 = 1) read strobe and write strobe (hmd0 = 1) timing requirement: t halp ale pulse width 10 ns t hasu had15-0 address setup before ale low 5 ns t hah had15-0 address hold after ale low 2 ns t hals start of write or read after ale low 1 10 ns t hsu hrw setup before start of write or read 1 5ns t hdsu had15-0 data setup before end of write 2 5ns t hwdh had15-0 data hold after end of write 2 3ns t hh hrw hold after end of write or read 2 3ns t hrwp read or write pulse width 3 20 ns switching characteristic: t hshk hack low after start of write or read 1 015ns t hkh hack hold after end of write or read 2 015ns t hde had15-0 data enabled after start of read 1 0ns t hdd had15-0 data valid after start of read 1 18 ns t hrdh had15-0 data hold after end of read 2 0ns t hrdd had15-0 data disabled after end of read 2 7ns notes 1 start of write or read = hds low and hsel low. 2 end of write or read = hds high and hsel high. 3 read or write pulse width = hds low and hsel low. t hkh ale t hrwp address t halp data t hsu t hwdh t hdsu hsel hack host write cycle had7? hrw t hals t hasu t hah t hh t hshk hds t hh ale t hrwp address t halp data t hshk t hkh t hde hsel hack host read cycle had7? hrw t hals t hasu t hah t hrdd t hdd t hsu t hrdh hds figure 24. host interface port (hmd1 = 1, hmd0 = 1)
ADSP-21MSP58/59 rev. 0 C35C environmental conditions ambient temperature rating: t amb = t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package q ja q jc q ca tqfp 50 c/w 2 c/w 48 c/w power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example: in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 5.0 v and t ck = 76.92 ns. total power dissipation = p int + (c v dd 2 f ) p int = internal power dissipation from power vs. frequency graph (figure 25). ( c v dd 2 f ) is calculated for each output: # of pins c v dd 2 f address, dms 8 10 pf 5 2 v 26 mhz = 52 mw data output, wr 9 10 pf 5 2 v 13 mhz = 30 mw rd 1 10 pf 5 2 v 13 mhz = 4 mw clkout 1 10 pf 5 2 v 26 mhz = 6 mw 92 mw total power dissipation for this example is p int + 92 mw. typical power consumption the typical power consumption can be calculated from the fol- lowing data, taken at 5.0 v and +25 c. dynamic v dd data was taken while executing 80% type 1 multifunction instructions, on random data. parameter typ i dd digital supply current (idle, codec powered up) 19 ma i dd digital supply current (idle) 13 ma i dd digital supply current (dynamic, codec powered up) 83 ma i dd digital supply current (dynamic) 78 ma i dd digital supply current (powerdown) 10 m a i cc analog supply current (dynamic) 15 ma analog devices re commends that the ADSP-21MSP58/59 is used with a 13 mhz input clock. below this input clock frequency, the codec performance changes and the performance specifications cannot be guaranteed. the codec filter character- istics, however, scale approximately linearly with frequency. if the codec is disabled, then the processor can be used at any allowed input frequency. the power consumption of the adsp- 21msp58/59 at these frequencies is shown in figure 25. 65mw 37mw 35mw 29mw 21mw 20mw 70 60 50 40 30 20 10 power, idle n modes 3 2 6 10 14 18 22 26 30 idles @ 5.0v codec inactive typical values idle (16) idle (32) idle (64) idle (128) 1/t ck ?mhz power (p idle n) ?mw power, idle 2 110 100 90 80 70 60 50 40 30 2 6 10 14 18 22 26 30 1/t ck ?mhz 100mw 83mw 69mw 57mw 49mw 42mw v dd = 5.5v v dd = 4.5v power (p idle ) ?mw idle 0 codec inactive max values v dd = 5.0v power, internal 1 480mw 391mw 310mw 191mw 154mw 118mw 550 500 450 400 350 300 250 200 150 100 50 2 6 10 14 18 22 26 30 power (p int ) ?mw v dd = 5.5v v dd = 4.5v 1/t ck ?mhz internal (80% nominal loading) codec inactive max values 550 500 450 400 350 300 250 200 150 100 50 v dd = 5.0v 1 2 3 valid for all temperature grades. power reflects device operating with no output loads. idle refers to ADSP-21MSP58/59 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. power reflects device operating with clkout disabled. typical power dissipation at 5.0v v dd during execution of idle n instruction (clock frequency reduction). power reflects device operating with clkout disabled. figure 25. power vs. internal processor frequency
rev. 0 C36C ADSP-21MSP58/59 capacitive loading figures 26 and 27 show the capacitive loading characteristics of the ADSP-21MSP58/59. c l ?pf rise time (0.4v ?2.4v) ?ns 28 0 25 175 50 75 100 125 150 24 16 12 8 4 20 v dd = 4.5v figure 26. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) c l ?pf +14 ? +12 +6 +2 nominal ? +10 +8 +4 25 175 50 75 100 125 150 valid output delay or hold ?ns figure 27. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) test conditions digital figure 28 shows the voltage reference levels and figure 29 shows the equivalent device loading for the ac measurements. 3.0v 1.5v 0.0v 2.0v 1.5v 0.8v input output figure 28. voltage reference levels for ac measure- ments (except output enable/disable) 50pf to output pin i oh i ol +1.5v figure 29. equivalent device loading for ac measure- ments (including all fixtures) analog figure 30 shows the analog test conditions. 2200pf npo 1.0? vin norm 2.2k w 2200pf npo 1.0? vin aux 2.2k w 1.0? decouple 0.1? ref_cap 10? figure 30. analog test conditions
ADSP-21MSP58/59 rev. 0 C37C output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured out- put high or low voltage to a high impedance state. the output disable time (t dis ) is the difference of t measured and t decay , as shown in the output enable/disable diagram. the time is the interval from when a reference signal reaches a high or low volt- age level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitative load, c l , and the cur- rent load, i l , on the output pin. it can be approximated by the following equation: t decay = c l 0.5 v i l from which t dis = t measured t decay is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. output enable time output pins are considered to be enabled when that have made a transition from a high-impedance state to when they start driv- ing. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. t m easured t dis t ena v oh (measured) reference signal v oh (measured) ?.5v v ol (measured) +0.5v t decay output stops driving v oh (measured) v ol (measured) output output starts here high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v ol (measured) 2.0v 1.0v figure 31. output enable/disable
rev. 0 C38C ADSP-21MSP58/59 pin configuration 100-lead thin plastic quad flatpack (tqfp) top view (pins down) 1 25 26 51 50 75 100 76 vinnorm decouple vinaux ref_filter gnda mmap reset irq2 hmd0 hmd1 hack fl0 sclk1 dr1/fi rfs1/ irw0 tfs1/ irq1 dt1/fo gnd sclk0 dr0 frs0 tfs0 dt0 vdd a13 d14 d13 d12 d11 d10 d9 d8 gnd d7 d6 d5 d4 d3 d2 d1 d0 bmode gnda voutn voutp vref vcc br pwd bg ha1 ha0 vdd gnd xtal clkin gnd vdd a0 a1 a2 a3 a4 a5 a6 a7 a8 a11 a12 hsel hwr / hds hrd /hrw clkout a9 a10 d15 d16 d17 d18 d19 d20 d21 d22 d23 vdd pms gnd hd7 hd6 hd5 hd4 hd3 hd2 hd1 hd0 ha2/ale dms bms rd wr
ADSP-21MSP58/59 rev. 0 C39C 100-lead thin plastic quad flatpack (tqfp) pinout tqfp pin tqfp pin tqfp pin tqfp pin number name number name number name number name 1 d15 26 ha1 51 a13 76 vcc 2 d16 27 ha0 52 vdd 77 vref 3 d17 28 hsel 53 dt0 78 voutp 4 d18 29 hwr/ hds 54 tfs0 79 voutn 5 d19 30 hrd /hrw 55 rfs0 80 gnd 6 d20 31 clkout 56 dr0 81 bmode 7 d21 32 vdd 57 sclk0 82 pwd 8 d22 33 gnd 58 gnd 83 br 9 d23 34 xtal 59 dt1/fo 84 bg 10 vdd 35 clkin 60 tfs1/ irq1 85 d0 11 gnd 36 gnd 61 rfs1/ irq0 86 d1 12 pms 37 vdd 62 dr1/fi 87 d2 13 dms 38 a0 63 sclk1 88 d3 14 bms 39 a1 64 fl0 89 d4 15 rd 40 a2 65 hack 90 d5 16 wr 41 a3 66 hmd1 91 d6 17 hd7 42 a4 67 hmd0 92 d7 18 hd6 43 a5 68 irq2 93 gnd 19 hd5 44 a6 69 reset 94 d8 20 hd4 45 a7 70 mmap 95 d9 21 hd3 46 a8 71 gnda 96 d10 22 hd2 47 a9 72 ref_filter 97 d11 23 hd1 48 a10 73 vinaux 98 d12 24 hd0 49 a11 74 decouple 99 d13 25 ha2/ale 50 a12 75 vinnorm 100 d14
rev. 0 C40C ADSP-21MSP58/59 ordering guide* ambient instruction temperate rate package package part number range (mips) description option ADSP-21MSP58bst-104 C40 c to +85 c 26 100-lead tqfp st-100 * refer to the section titled ordering procedure for adsp-21msp59 rom processors for information about ordering rom coded parts. printed in u.s.a. c2030C4C4/95 outline dimensions dimensions shown in millimeters and (inches) 100-lead metric thin plastic quad flat pack (tqfp) seating plane 0.75 (0.030) 0.50 (0.019) 1.60 (0.063) max 0.15 (0.006) 0.05 (0.002) 0.057 (1.45) 0.053 (1.35) 0.1 (0.004) top view (pins down) 1 25 26 51 50 75 100 76 0.27 (0.011) 0.17 (0.007) 16.25 (0.640) 15.75 (0.620) sq 14.05 (0.553) 13.95 (0.549) sq 0.56 (0.022) 0.44 (0.018) 12.06 (0.475) sq

▲Up To Search▲

Price & Availability of ADSP-21MSP58

	To Download ADSP-21MSP58 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .